Abstract

In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial …

Legal parties

Party
Inventors (applicants): Chun Hung Pang, Kuan Loon Tan, Wee Hoo Cheah
Assignees (initial): Intel Corporation (Santa Clara, US)
Agents: Jordan IP Law, LLC (attorney)

The application was examined by Raymond Phan (USPTO dept. 2111)

Claims

  • 1. A serial bus interface circuit, comprising: …
  • 2. The serial bus interface circuit of claim 1 , wherein the lookup table is updated …
  • 3. The serial bus interface circuit of claim 1 , wherein the lookup table is updated …

Cited documents

Patents

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Drawings

Brief Description of the Drawings

Various features of the invention will be apparent from the following description of preferred embodiments as illustrated in the accompanying drawings, in which like reference numerals generally refer to the same …

Description

Background and Related Art

Many electronic devices utilize serial …

Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough …

More details about Method and Apparatus to Reduce Serial Bus Transmission Power

Miscellaneous patent data

Categorized under Arbitration as a primary classification, developed by Wee Hoo Cheah et al., the published inventor's name is Wee Hoo Cheah, the application number is 12/928,334 (U.S.), the patent is illustrated by 4 drawings, the grant publication date is Dec. 31, 2013, the applicant's last name is Pang, and his first name is Chun Hung, the protection scope is defined by 9 claims, the known agent - Jordan IP Law, LLC, the claim 1 is exemplary as chosen by the examiner, the application was published on Dec. 9, 2010, an application examiner - Raymond Phan (2111 USPTO department), the exemplary patent drawings are Block diagram of an electronic, Block diagram of a serial, Method and Apparatus to Reduce, Flow diagram, the invention is titled Method and Apparatus to Reduce Serial Bus Transmission Power, the assignee organization is Intel Corporation, located in Santa Clara (US), the patent extension term is 118 days, the assignee is categorized as a United States company, similar classification categories are Time-slot accessing, Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers, Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities, Programme initiating, Programme switching, e.g. by interrupt, in storage media based on magnetic or optical technology, e.g. disks with sectors, in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other, Multimode interrupt processing, Hot docking, Buffer or que control, Card insertion, the grant number is 08621129, the invention details are shown in 5 figures, particularly claims a serial bus interface circuit, comprising…

Invention classification information

The invention is classified under Intelligent bridge, for access to common bus or bus system, Bus structure, Arbitration, Common protocol.

Patent details
Publication number 08621129
Publication date Dec. 31, 2013
Kind code B2
Application number 12/928,334
Application date Dec. 9, 2010
Application type U
Application series code 12
Extension term 118
National classification 710/309
Total number of claims 9
Exemplary claims 1
Number of drawings 4
Number of figures 5
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