Featured patents

Method and Apparatus of Core Timing Prediction of Core Logic in the Chip-Level Implementation Process Through an Over-Core Window on a Chip-Level Routing Layer
US 08775995 B2, July 8, 2014, Timing Analysis, Ruben Salvador Molina et al. / LSI Corporation (Milpitas, US)
A method of a chip-level implementation process, comprising:…

Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling
US 08732627 B2, May 20, 2014, Design of Semiconductor Mask or Reticle, Jingrui He et al. / International Business Machines Corporation (Armonk, US)
A method for performing enhanced wafer quality prediction in a semiconductor…

Layout Determination
US 08694932 B2, April 8, 2014, Logic circuit synthesis (mapping logic), Edward Merritt et al. / Empire Technology Development LLC (Wilmington, US)
A device comprising:…

Group Bounding Box Region-Constrained Placement for Integrated Circuit Design
US 08701070 B2, April 15, 2014, Floorplanning, Yun-Han Lee et al. / Taiwan Semiconductor Manufacturing Company Limited (Hsin-Chu, TW)
A method, comprising:…

System and Method for Designing Cell Rows With Differing Cell Heights
US 08631377 B2, Jan. 14, 2014, With partitioning, Yun-Han Lee et al. / Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW)
An integrated circuit comprising:…

Methods, Systems, and Articles of Manufacture for Implementing a Physical Design of an Electronic Circuit With Automatic Snapping
US 08595662 B1, Nov. 26, 2013, Physical design processing, Henry Yu et al. / Cadence Design Systems, Inc. (San Jose, US)
A computer implemented method for implementing a physical design of an electronic…

Routability Using Multiplexer Structures
US 08539400 B2, Sept. 17, 2013, Logic circuit synthesis (mapping logic), Zhuo Li et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system comprising at least one…

Spatial Map of Mask-Pattern Defects
US 08510683 B2, Aug. 13, 2013, Defect (including design rule checking), Xin Zhou et al. / Synopsys, Inc. (Mountain View, US)
A computer-implemented method for providing a spatial map of defects in at least…

Modeling and Simulating the Impact of Imperfectly Patterned via Arrays on Integrated Circuits
US 08468482 B1, June 18, 2013, Physical design processing, Robert C. Pack et al. / Worldwide Pro Ltd. (Hong Kong, CN)
A method comprising:…

Alignment Net Insertion for Straightening the Datapath in a Force-Directed Placer
US 08453093 B2, May 28, 2013, Constraint-based, Natarajan Viswanathan et al. / International Business Machines Corporation (Armonk, US)
A method of placing cells in a layout of an integrated circuit design,…

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