Featured patents

Method and Apparatus for Enhancing Signal Strength for Improved Generation and Placement of Model-Based Sub-Resolution Assist Features (MB-SRAF)
US 08826198 B2, Sept. 2, 2014, Layout generation (polygon, pattern feature), Yen-Wen Lu et al. / ASML Netherlands B.V. (Veldhoven, NL)
A method implemented by a computer for placing sub-resolution assist features…

Adaptive Patterning for Panelized Packaging
US 08826221 B2, Sept. 2, 2014, System-on-chip design, Timothy L. Olson et al. / DECA Technologies Inc. (Tempe, US)
A method of making a plurality of semiconductor packages, comprising:…

ESD Analysis Apparatus
US 08819614 B2, Aug. 26, 2014, Testing or Evaluating, Sachio Hayashi / Kabushiki Kaisha Toshiba (Tokyo, JP)
An ESD analysis apparatus, comprising:…

IC Layout Parsing for Multiple Masks
US 08713483 B2, April 29, 2014, Design of Semiconductor Mask or Reticle, Le Hong et al. / Mentor Graphics Corporation (Wilsonville, US)
A method of preparing layout data with a computer to create two or more…

System and Method to Generate Re-Useable Layout Components From Schematic Components in an IC Design With Hierarchical Parameters
US 08719754 B1, May 6, 2014, Placement or layout, Arnold Ginetti / Cadence Design Systems, Inc. (San Jose, US)
A method to align poly features within chain sets in an integrated circuit layout…

Managing and Controlling the Use of Hardware Resources on Integrated Circuits
US 08726204 B2, May 13, 2014, Logic circuit synthesis (mapping logic), Darren Zacher et al. / Mentor Graphics Corporation (Wilsonville, US)
One or more non-transitory computer-readable media storing computer-executable…

Circuit Design Support Computer Product, Method, and Apparatus
US 08677296 B2, March 18, 2014, Physical design processing, Kazuhiko Hatae / Fujitsu Limited (Kawasaki, JP)
A non-transitory computer-readable recording medium storing a design support…

Processing Condition Determining Method and Apparatus, Display Method and Apparatus, Processing Apparatus, Measurement Apparatus and Exposure Apparatus, Substrate Processing System, and Program and Information Recording Medium
US 08566756 B2, Oct. 22, 2013, Manufacturing optimizations, Shinichi Okita / Nikon Corporation (Tokyo, JP)
A processing condition determining method comprising:…

Encrypted Profiles for Parasitic Extraction
US 08499263 B1, July 30, 2013, Integrated Circuit Design Processing, Weiping Shi et al. / Mentor Graphics Corporation (Wilsonville, US)
A method of generating encrypted profiles for layout features, comprising:…

Automated Lithographic Hot Spot Detection Employing Unsupervised Topological Image Categorization
US 08453075 B2, May 28, 2013, Defect (including design rule checking), Wei Guo et al. / International Business Machines Corporation (Armonk, US)
A method of modifying lithographic hot spots in a chip design layout comprising:…

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