Featured patents

Verifying Data Intensive State Transition Machines Related Application
US 08756543 B2, June 17, 2014, Design verification (functional simulation, model checking), Jun Sawada et al. / International Business Machines Corporation (Armonk, US)
A computer implemented method for verifying a state transition machine (STM),…

Method of On-Board Wiring
US 08745562 B2, June 3, 2014, Noise, Makoto Tanaka et al. / DENSO CORPORATION (Kariya, JP)
A design method of on-board wiring in a designed circuit, the method comprising:…

Method and Apparatus for Utilizing Constraints for the Routing of a Design on a Programmable Logic Device
US 08745566 B1, June 3, 2014, PLDs, Caroline Pantofaru et al. / Altera Corporation (San Jose, US)
A system designer, comprising:…

Sequential Sizing in Physical Synthesis
US 08683408 B2, March 25, 2014, Timing Analysis, Mahesh A. Iyer et al. / Synopsys, Inc. (Mountain View, US)
A method for optimizing a circuit design, the method comprising:…

Simultaneous Multi-Corner Static Timing Analysis Using Samples-Based Static Timing Infrastructure
US 08615727 B2, Dec. 24, 2013, For timing, Feroze P. Taraporevala et al. / Synopsys, Inc. (Mountain View, US)
A method of performing simultaneous multi-corner static timing analysis (STA)…

Flexible Noise and Delay Modeling of Circuit Stages for Static Timing Analysis of Integrated Circuit Designs
US 08595669 B1, Nov. 26, 2013, Noise, Igor Keller et al. / Cadence Design Systems, Inc. (San Jose, US)
A system for static noise analysis of an integrated circuit design, the system…

Method for Placement and Routing of a Circuit Design
US 08522185 B1, Aug. 27, 2013, Routing, Robert M. Balzli, Jr. / Xilinx, Inc. (San Jose, US)
A processor-implemented method for placement and routing of a circuit design,…

Method of Designing a Template Pattern, Method of Manufacturing a Template and Method of Manufacturing a Semiconductor Device
US 08468480 B2, June 18, 2013, Physical design processing, Ryoichi Inanami et al. / Kabushiki Kaisha Toshiba (Tokyo, JP)
A computer-implemented method of designing a template pattern used for imprint…

System and Method for Metastability Verification of Circuits of an Integrated Circuit
US 08448111 B2, May 21, 2013, Timing verification (timing analysis), Ashish Bansal et al. / Atrenta, Inc. (San Jose, US)
A method for metastability verification of an integrated circuit design (IC),…

Method and an Apparatus to Perform Statistical Static Timing Analysis
US 08448104 B1, May 21, 2013, Yield, Harish Kriplani et al. / Cadence Design Systems, Inc. (San Jose, US)
A system comprising:…

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