Featured patents

Multiple via Connections Using Connectivity Rings
US 08813016 B1, Aug. 19, 2014, Power (voltage islands), Hui-Zhong Zhuang et al. / Taiwan Semiconductor Manufacturing Company Limited (Hsin-Chu, TW)
A method for performing design layout, comprising:…

Producing a Net Topology Pattern as a Constraint Upon Routing of Signal Paths in an Integrated Circuit Design
US 08806405 B2, Aug. 12, 2014, Routing, Jeffrey Markham et al. / Cadence Design Systems, Inc. (San Jose, US)
A method to produce in a computer readable storage device constraint information…

Methods for Modeling of FinFET Width Quantization
US 08799848 B1, Aug. 5, 2014, Testing or Evaluating, Richard Q. Williams et al. / International Business Machines Corporation (Armonk, US)
A method for modeling fin field effect transistor (FinFET) width quantization,…

System and Method for Designing Digital Circuitry With an Activity Sensor
US 08782592 B2, July 15, 2014, Testing or Evaluating, Pascal Benoit et al. / Commissariat a l'Energie Atomique et aux Energies Alternatives (Paris, FR)
A system for designing digital circuitry comprising:…

Hierarchical Layout Versus Schematic (LVS) Comparison With Extraneous Device Elimination
US 08751985 B1, June 10, 2014, Design verification (functional simulation, model checking), Sandeep Puri et al. / Globalfoundries Inc. (Santa Clara, US)
A method comprising:…

Methods of Designing Semiconductor Devices and Methods of Modifying Layouts of Semiconductor Devices
US 08621399 B2, Dec. 31, 2013, Defect (including design rule checking), Jung-Yun Choi et al. / Samsung Electronics Co., Ltd. (Gyeonggi-do, KR)
A method of designing a semiconductor device, the method comprising:…

Semiconductor Device Feature Density Gradient Verification
US 08549453 B2, Oct. 1, 2013, Verification, Young-Chow Peng et al. / Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW)
A method for verifying densities in a semiconductor device layout, said method…

Zone-Based Area Recovery in Electronic Design Automation
US 08527927 B2, Sept. 3, 2013, Timing Analysis, Mahesh A. Iyer et al. / Synopsys, Inc. (Mountain View, US)
A computer-implemented method for facilitating the creation of a design…

Register Transfer Level Design Compilation Advisor
US 08516411 B2, Aug. 20, 2013, Translation (logic-to-logic, logic-to-netlist, netlist processing), Charles W. Selvidge et al. / Mentor Graphics Corporation (Wilsonville, US)
A computer implemented method of compiling a circuit design for emulation…

Method and Device for Selectively Adding Timing Margin in an Integrated Circuit
US 08490045 B2, July 16, 2013, Testing or Evaluating, Paul S. Zuchowski et al. / International Business Machines Corporation (Armonk, US)
A method for testing an integrated circuit, comprising:…

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