Featured patents

Automatic Clock Tree Synthesis Exceptions Generation
US 08843872 B1, Sept. 23, 2014, Optimization, Ssu-Min Chang et al. / Synopsys, Inc. (Mountain View, US)
A method for generating clock tree synthesis (CTS) exceptions for a circuit…

Test Bench Hierarchy and Connectivity in a Debugging Environment
US 08782581 B2, July 15, 2014, Design verification (functional simulation, model checking), Tarak Parikh et al. / Mentor Graphics Corporation (Wilsonville, US)
A method comprising:…

Software Debugging of Synthesized Hardware
US 08775986 B1, July 8, 2014, Logic circuit synthesis (mapping logic), L. James Hwang et al. / Xilinx, Inc. (San Jose, US)
A method for synthesizing a high-level language (HLL) program, comprising:…

Method of Designing Pattern Layouts
US 08694927 B2, April 8, 2014, Optical proximity correction (including RET), Moon-Gyu Jeong / Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR)
A method of designing a pattern layout, the method comprising:…

Modeling the Total Parasitic Resistances of the Source/Drain Regions of a Multi-Fin Multi-Gate Field Effect Transistor
US 08689166 B2, April 1, 2014, Routing, Ning Lu / International Business Machines Corporation (Armonk, US)
A modeling method comprising:…

Double Patterning Compatible Colorless M1 Route
US 08677291 B1, March 18, 2014, Layout generation (polygon, pattern feature), Jongwook Kye et al. / GlobalFoundries Inc. (Grand Cayman, KY)
A method comprising:…

Small, Adaptable, Real-Time, Scalable Image Processing Chip
US 08601421 B2, Dec. 3, 2013, Mapping circuit design to programmable logic devices (PLDs), Jennifer K. Park et al. / Lockheed Martin Corporation (Bethesda, US)
A programmable chip device comprising:…

System and Method for Designing Integrated Circuits That Employ Adaptive Voltage Scaling Optimization
US 08539424 B2, Sept. 17, 2013, For timing, Alexander Tetelbaum / LSI Corporation (Milpitas, US)
A design process system for designing a circuit, comprising:…

Vertical Power Budgeting and Shifting for Three-Dimensional Integration
US 08516426 B2, Aug. 20, 2013, Power distribution, Phillip J. Restle et al. / International Business Machines Corporation (Armonk, US)
A method for managing power distribution on a three-dimensional chip stack having…

Method for Compensating for Variations in Structures of an Integrated Circuit
US 08458628 B2, June 4, 2013, Layout generation (polygon, pattern feature), Bruce Walter Porth et al. / International Business Machines Corporation (Armonk, US)
A method, comprising:…

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