Featured patents

Modeling Gate Size Range by Using a Penalty Function in a Numerical Gate Sizing Framework
US 08826217 B2, Sept. 2, 2014, Optimization, Amir H. Mottaez et al. / Synopsys, Inc. (Mountain View, US)
A method for modeling gate size range by using a penalty function, the method…

Efficient Configuration of an Integrated Circuit Device Using High-Level Language
US 08806403 B1, Aug. 12, 2014, Mapping circuit design to programmable logic devices (PLDs), Dmitry N. Denisenko et al. / Altera Corporation (San Jose, US)
A method of configuring an integrated circuit device using a high-level language,…

Photolithography Capacity Planning System and Non-Transitory Computer Readable Media Thereof
US 08863047 B1, Oct. 14, 2014, Manufacturing optimizations, Chen-Fu Chien et al. / National Tsing Hua University (Hsinchu, TW)
A photolithography capacity planning system, comprising:…

Method and Apparatus of Core Timing Prediction of Core Logic in the Chip-Level Implementation Process Through an Over-Core Window on a Chip-Level Routing Layer
US 08775995 B2, July 8, 2014, Timing Analysis, Ruben Salvador Molina et al. / LSI Corporation (Milpitas, US)
A method of a chip-level implementation process, comprising:…

Automatic Reduction of Modes of Electronic Circuits for Timing Analysis
US 08701074 B2, April 15, 2014, For timing, Subramanyam Sripada et al. / Synopsys, Inc. (Mountain View, US)
A computer-implemented method for identifying modes from a plurality of modes…

Wiring Design Apparatus and Method
US 08667447 B2, March 4, 2014, Routing, Toshiyasu Sakata et al. / Fujitsu Limited (Kawasaki, JP)
A routing path creation supporting method, comprising:…

Systems and Methods of Designing Integrated Circuits
US 08661389 B2, Feb. 25, 2014, Floorplanning, Li-Chun Tien et al. / Taiwan Semiconductor Manufacturing Company, Ltd. TW
A method of designing an integrated circuit, the method comprising:…

Systems and Methods for Fixing Pin Mismatch in Layout Migration
US 08627247 B1, Jan. 7, 2014, Translation (logic-to-logic, logic-to-netlist, netlist processing), Matthew T. Guzowski et al. / International Business Machines Corporation (Armonk, US)
A method comprising:…

Bonding Controller Guided Assessment and Optimization for Chip-To-Chip Stacking
US 08543959 B2, Sept. 24, 2013, Optimization, Gary Dale Carpenter et al. / International Business Machines Corporation (Armonk, US)
A computer implemented method for performance-based chip-to-chip stacking,…

Retargeting for Electrical Yield Enhancement
US 08495530 B2, July 23, 2013, Yield, Kanak B. Agarwal / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for electrical yield enhancement…

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