Featured patents

Accurate Approximation of the Objective Function for Solving the Gate-Sizing Problem Using a Numerical Solver
US 08826218 B2, Sept. 2, 2014, Optimization, Mahesh A. Iyer et al. / Synopsys, Inc. (Mountain View, US)
A method for optimizing a circuit design, the method comprising:…

Layout Decomposition Method and Apparatus for Multiple Patterning Lithography
US 08799844 B2, Aug. 5, 2014, Mapping circuit design to programmable logic devices (PLDs), Xiaoping Tang et al. / International Business Machines Corporation (Armonk, US)
A method comprising:…

System and Method for Design, Procurement and Manufacturing Collaboration
US 08806398 B2, Aug. 12, 2014, Design entry, Douglas Edward Maddox et al. / Flextronics AP, LLC (San Jose, US)
An electronically-readable storage medium having stored therein a data structure…

System for Simplifying Layout Processing
US 08782574 B2, July 15, 2014, Layout generation (polygon, pattern feature), Youping Zhang et al.
An integrated circuit design layout processing system having computer software…

Circuit Macro Placement Using Macro Aspect Ratio Based on Ports
US 08762919 B2, June 24, 2014, With partitioning, Thomas Ludwig et al. / International Business Machines Corporation (Armonk, US)
A computer implemented method for placement of random logic macros…

Pattern Matching Optical Proximity Correction
US 08683394 B2, March 25, 2014, Optical proximity correction (including RET), Mark C Simmons / Mentor Graphics Corporation (Wilsonville, US)
A method of pattern matching optical proximity correction, comprising:…

Function Symmetry-Based Optimization for Physical Synthesis of Programmable Integrated Circuits
US 08667435 B1, March 4, 2014, Translation (logic-to-logic, logic-to-netlist, netlist processing), Tetse Jang et al. / Xilinx, Inc. (San Jose, US)
A computer-implemented method of implementing a circuit design within…

Method and System for Schematic-Visualization Driven Topologically-Equivalent Layout Design in RFSiP
US 08601422 B2, Dec. 3, 2013, Constraint-based, Utpal Bhattacharya et al. / Cadence Design Systems, Inc. (San Jose, US)
A computer implemented method for creating a layout of an electrical design,…

T-Coil Network Design for Improved Bandwidth and Electrostatic Discharge Immunity
US 08453092 B2, May 28, 2013, Power distribution, Toan D. Tran et al. / Xilinx, Inc. (San Jose, US)
A circuit, comprising:…

System and Method for Series and Parallel Combinations of Electrical Elements
US 08453097 B2, May 28, 2013, Optimization, A. Martin Mallinson / ESS Technology, Inc. (Fremont, US)
A method of designing semiconductor circuit components having nominal values…

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