Featured patents

Method and System for Performing Invariant-Guided Abstraction of a Logic Design
US 08850372 B2, Sept. 30, 2014, Design verification (functional simulation, model checking), Hari Mony et al. / International Business Machines Corporation (Armonk, US)
A computer-implemented method of invariant-guided abstraction within a design…

Micro Electro Mechanical Switch System and Method for Testing and Configuring Semiconductor Functional Circuits
US 08732644 B1, May 20, 2014, Configuring PLDs (including data file, bitstream generation, etc.), Michael B. Diamond / Nvidia Corporation (Santa Clara, US)
An integrated circuit comprising:…

Dynamic Frequency Control Using Coarse Clock Gating
US 08671380 B2, March 11, 2014, For power, James Wang et al. / Apple Inc. (Cupertino, US)
An apparatus comprising:…

Method and System for Searching for Graphical Objects of a Design
US 08640078 B2, Jan. 28, 2014, Layout editor (with ECO, reuse, GUI), Chayan Majumder et al. / Cadence Design Systems, Inc. (San Jose, US)
A method for searching for graphical objects in a graphical circuit design using…

Method and System for High Speed and Low Memory Footprint Static Timing Analysis
US 08627250 B2, Jan. 7, 2014, Timing verification (timing analysis), Chin-Wei Jim Chang et al. / Synopsys, Inc. (Mountain View, US)
A computer-implemented method for performing static timing analysis of a circuit…

Multi-Voltage Domain Circuit Design Verification Method
US 08601426 B1, Dec. 3, 2013, For power, Huabin Du / Freescale Semiconductor, Inc. (Austin, US)
A method of identifying one or more missing level shifters in a multi-voltage…

Method and Apparatus for Implementing a Parameterizable Filter Block With an Electronic Design Automation Tool
US 08499262 B1, July 30, 2013, Integrated Circuit Design Processing, Steven Perry / Altera Corporation (San Jose, US)
An electric design automation (EDA) tool for generating a design of a system…

Standard Cells Having Transistors Annotated for Gate-Length Biasing
US 08490043 B2, July 16, 2013, Optimization, Puneet Gupta et al. / Tela Innovations, Inc. (Los Gatos, US)
A standard cell library stored on a computer readable storage, the standard cell…

Lithography Modeling and Applications
US 08479125 B2, July 2, 2013, Design of Semiconductor Mask or Reticle, Christophe Pierrat
A method of building an image representation for use in semiconductor processes,…

Method and System for Scalable Reduction in Registers With SAT-based Resubstitution
US 08473882 B2, June 25, 2013, Design verification (functional simulation, model checking), Hari Mony et al. / International Business Machines Corporation (Armonk, US)
A computer-implemented method for reducing the size of a logic network design,…

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