Featured patents

Method for Manufacturing Semiconductor Device on the Basis of Changed Design Layout Data
US 08789002 B2, July 22, 2014, Optimization, Takuji Tanaka / Fujitsu Semiconductor Limited (Yokohama, JP)
A method of manufacturing a semiconductor device comprising:…

Current-Aware Floorplanning to Overcome Current Delivery Limitations in Integrated Circuits
US 08863068 B2, Oct. 14, 2014, For power, John A. Darringer et al. / International Business Machines Corporation (Armonk, US)
A method for integrated circuit (IC) chip and IC package design comprising:…

Configurable Circuit and Mesh Structure for Integrated Circuit
US 08645892 B1, Feb. 4, 2014, Detailed, Vishal Gupta et al. / Freescale Semiconductor, Inc. (Austin, US)
An integrated circuit (IC) layout, comprising:…

Solving Congestion Using Net Grouping
US 08601425 B2, Dec. 3, 2013, Global, Charles Jay Alpert et al. / International Business Machines Corporation (Armonk, US)
A computer implemented method for solving a congestion problem in an integrated…

Photomask Manufacturing Method and Semiconductor Device Manufacturing Method
US 08584054 B2, Nov. 12, 2013, Design of Semiconductor Mask or Reticle, Kazuya Fukuhara et al. / Kabushiki Kaisha Toshiba (Tokyo, JP)
A photomask manufacturing apparatus, comprising:…

Graphic Rendering of Circuit Positions
US 08566775 B2, Oct. 22, 2013, Testing or Evaluating, Joseph David Shulmister, Jr. / Verizon Patent and Licensing Inc. (Basking Ridge, US)
A device comprising:…

Verification of Soft Error Resilience
US 08555234 B2, Oct. 8, 2013, Testing or Evaluating, Mark Anthony Check et al. / International Business Machines Corporation (Armonk, US)
A method for verification of soft error resilience of devices from design data…

System and Method for Modifying a Data Set of a Photomask
US 08572517 B2, Oct. 29, 2013, Design of Semiconductor Mask or Reticle, Abdurrahman Sezginer et al. / Cadence Design Systems, Inc. (San Jose, US)
A method for optical compensation comprising:…

Selection of Optimum Patterns in a Design Layout Based on Diffraction Signature Analysis
US 08543947 B2, Sept. 24, 2013, Layout generation (polygon, pattern feature), Hong Chen et al. / ASML Netherlands B.V. (Veldhoven, NL)
A method implemented by a computer, the method being of selecting a subset…

Application of a Relational Database in Integrated Circuit Design
US 08516418 B2, Aug. 20, 2013, Design verification (functional simulation, model checking), Aman U. Joshi et al. / Oracle America, Inc. (Redwood City, US)
A method, comprising:…

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