Featured patents

Processor With Increased Efficiency via Control Word Prediction
US 08819397 B2, Aug. 26, 2014, Processing Control, Jay Fleischman et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method, comprising:…

Fast Remote Communication and Computation Between Processors Using Store and Load Operations on Direct Core-To-Core Memory
US 08799625 B2, Aug. 5, 2014, Interface, Karthick Rajamani et al. / International Business Machines Corporation (Armonk, US)
A computer implemented method for fast remote communication and computation…

Method and System for Hardware-Based Security of Object References
US 08732442 B2, May 20, 2014, Instruction modification based on condition, Gregory M. Wright et al. / Oracle America, Inc. (Redwood City, US)
A method for managing data, comprising:…

Mechanism for Conflict Detection Using SIMD
US 08688957 B2, April 1, 2014, Single instruction, multiple data (SIMD), Victor W. Lee et al. / Intel Corporation (Santa Clara, US)
A method of conflict detection, the method comprising:…

Processor With Support for Nested Speculative Sections With Different Transactional Modes
US 08621183 B2, Dec. 31, 2013, Commitment control or register bypass, David S. Christie et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A system, comprising:…

Apparatus and Method for Generating VLIW, and Processor and Method for Processing VLIW
US 08601244 B2, Dec. 3, 2013, Instruction modification based on condition, Bernhard Egger et al. / Samsung Electronics Co., Ltd. (Suwon-si, KR)
A very long instruction word (VLIW) processor comprising:…

Odd and Even Start Bit Vectors
US 08589661 B2, Nov. 19, 2013, Decoding instruction to accommodate variable length instruction or operand, Steven Beigelmacher et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method for processing a stream of information, comprising:…

Runtime Extraction of Data Parallelism
US 08583905 B2, Nov. 12, 2013, Loop execution, Alexandre E. Eichenberger et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for extracting data dependencies during…

Vector Processing of Different Instructions Selected by Each Unit From Multiple Instruction Group Based on Instruction Predicate and Previous Result Comparison
US 08566566 B2, Oct. 22, 2013, Of multiple instructions simultaneously, Moo Kyoung Chung et al. / Electronics and Telecommunications Research Institute (Daejeon, KR)
A vector processing apparatus, comprising:…

Mixed Torus and Hypercube Multi-Rank Tensor Expansion Method
US 08510535 B2, Aug. 13, 2013, Array processor element interconnection, Yuefan Deng et al. / Shanghai Redneurons Co., Ltd (Shanghai, CN)
A method for expansion of a cube, integrated with supernodes, each supernode…

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