Featured patents

Selective Routing of Local Memory Accesses and Device Thereof
US 08756405 B2, June 17, 2014, Processing control for data transfer, William C. Moyer / Freescale Semiconductor, Inc. (Austin, US)
A method comprising:…

Processor for Concurrently Executing Plural Instruction Streams
US 08745359 B2, June 3, 2014, Long instruction word, Shohei Nomoto / NEC Corporation (Tokyo, JP)
A processor executing a very long instruction word containing a plurality…

Programming Language Exposing Idiom Calls to a Programming Idiom Accelerator
US 08725992 B2, May 13, 2014, Processing Control, Ravi K. Arimilli et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for performing programming idiom…

Processor Micro-Architecture for Compute, Save or Restore Multiple Registers, Devices, Systems, Methods and Processes of Manufacture
US 08713293 B2, April 29, 2014, Loop execution, Yuji Umemoto et al. / Texas Instruments Incorporated (Dallas, US)
A processor for electronic computing comprising:…

Detecting Branch Direction and Target Address Pattern and Supplying Fetch Address by Replay Unit Instead of Branch Prediction Unit
US 08667257 B2, March 4, 2014, Prefetching a branch target, Anthony X. Jarvis et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A processor, comprising:…

Method and System for Packet Processing
US 08639912 B2, Jan. 28, 2014, Array processor, Stephen J. Davis et al. / Mosaid Technologies Incorporated (Ottawa, CA)
A data processing system, comprising:…

Massively Parallel Processing Core With Plural Chains of Processing Elements and Respective Smart Memory Storing Select Data Received From Each Chain
US 08583896 B2, Nov. 12, 2013, Particular data driven memory structure, Srimat Chakradhar et al. / NEC Laboratories America, Inc. (Princeton, US)
An accelerator system, comprising:…

Cache And/Or Socket Sensitive Multi-Processor Cores Breadth-First Traversal
US 08533432 B2, Sept. 10, 2013, Application specific, Jatin Chhugani et al. / Intel Corporation (Santa Clara, US)
At least one non-transitory computer-readable storage device having a plurality…

Reordering Operands Assigned to Each One of Read Request Ports Concurrently Accessing Multibank Register File to Avoid Bank Conflict
US 08533435 B2, Sept. 10, 2013, Instruction Issuing, Yan Yan Tang et al. / NVIDIA Corporation (Santa Clara, US)
A method for collecting operands specified by instructions, comprising:…

Parallel Pipelined Vector Reduction in a Data Processing System
US 08447954 B2, May 21, 2013, Distributed processing system, Bin Jia / International Business Machines Corporation (Armonk, US)
A method of vector reduction in a parallel processing data processing system,…

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