Featured patents

Micro Grid Tiered Computing System With Plurality of Complex Shape Structures Interconnected by Bridge Modules in Docking Bays
US 08819395 B2, Aug. 26, 2014, Distributed processing system, Ian E. Oakenfull / International Business Machines Corporation (Armonk, US)
A micro grid apparatus for use in a mainframe system or server system,…

Programmable Event Driven Yield Mechanism Which May Activate Other Threads
US 08868887 B2, Oct. 21, 2014, Context preserving (e.g., context swapping, checkpointing, register windowing, John Shen et al. / Intel Corporation (Santa Clara, US)
A multithreaded processor additionally supporting virtual multithreading,…

Register File System and Method for Pipelined Processing
US 08725991 B2, May 13, 2014, Architecture Based Instruction Processing, Suresh Venkumahanti et al. / QUALCOMM Incorporated (San Diego, US)
A processor comprising:…

Gather Cache Architecture
US 08688962 B2, April 1, 2014, Processing control for data transfer, Shlomo Raikin et al. / Intel Corporation (Santa Clara, US)
A processor comprising:…

Asynchronous Pipelined Data Path With Data Transition
US 08677103 B1, March 18, 2014, Processing control for data transfer, Dror Barash / Marvell Isreal (M.I.S.L) Ltd. (Yokneam, IL
An apparatus comprising:…

Register Renaming Table Recovery Method and System for Use in a Processor
US 08583900 B2, Nov. 12, 2013, Scoreboarding, reservation station, or aliasing, Chun-Wang Wei et al. / RDC Semiconductor Co., Ltd. (Hsinchu, TW)
A register renaming table recovery method for use in a processor, the register…

Lane Crossing Instruction Selecting Operand Data Bits Conveyed From Register via Direct Path and Lane Crossing Path for Execution
US 08560811 B2, Oct. 15, 2013, Decoding instruction to accommodate variable length instruction or operand, John M. King / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method, comprising:…

Processing Vectors Using Wrapping Shift Instructions in the Macroscalar Architecture
US 08549265 B2, Oct. 1, 2013, Floating point or vector, Jeffry E. Gonion / Apple Inc. (Cupertino, US)
A method, comprising:…

Scalar/Vector Processor That Includes a Functional Unit With a Vector Section and a Scalar Section
US 08510534 B2, Aug. 13, 2013, Scalar / vector processor interface, Nur Engin et al. / ST-Ericsson SA (Plan-les-Ouates, CH)
A scalar/vector processor comprising:…

Performing Escape Actions in Transactions
US 08489864 B2, July 16, 2013, Processing Control, Bratin Saha et al. / Microsoft Corporation (Redmond, US)
In a computing environment, a method of performing hardware based transactions,…

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