Featured patents

Technique to Perform Three-Source Operations
US 08825989 B2, Sept. 2, 2014, Processing Control, Stephan Jourdan et al. / Intel Corporation (Santa Clara, US)
A processor comprising:…

Technique for Simulating Floating-Point Stack Operation Involving Conversion of Certain Floating-Point Register Numbers Based on a Top-Of-Stack Pointer and Modulo Function
US 08788796 B2, July 22, 2014, Specialized instruction processing in support of testing, debugging, emulation, Xiaoyu Li et al. / Loongson Technology Corporation Limited (Beijing, CN)
A Reduced Instruction Set Computing (RISC) processor comprising:…

Method and System for Controlling Message Traffic Between Two Processors
US 08751774 B2, June 10, 2014, Including coprocessor, Wan-ping Yang et al. / DENSO International America, Inc. (Southfield, US)
A system configured to control messaging traffic between a first processor…

Architecture and Programming in a Parallel Processing Environment With Switch-Interconnected Processors
US 08656141 B1, Feb. 18, 2014, Array processor, Anant Agarwal / Massachusetts Institute of Technology (Cambridge, US)
An integrated circuit comprising:…

Communication System and Its Method and Communication Apparatus and Its Method
US 08601243 B2, Dec. 3, 2013, Processing control for data transfer, Akihoro Morohashi / Sony Corporation (Tokyo, JP)
An information communication system comprising:…

Diagnose Instruction for Serializing Processing
US 08595469 B2, Nov. 26, 2013, Processing Control, Lisa C. Heller / International Business Machines Corporation (Armonk, US)
A computer program product for executing a diagnose instruction to serialize…

Odd and Even Start Bit Vectors
US 08589661 B2, Nov. 19, 2013, Decoding instruction to accommodate variable length instruction or operand, Steven Beigelmacher et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method for processing a stream of information, comprising:…

Apparatus for Efficiently Determining Instruction Length Instruction Within a Stream of X86 Instruction Bytes
US 08533434 B2, Sept. 10, 2013, Decoding instruction to accommodate variable length instruction or operand, John L. Duncan et al. / VIA Technologies, Inc. (New Taipei, TW)
A method for efficiently determining the length of an instruction within a stream…

Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
US 08489858 B2, July 16, 2013, Array processor operation, Edwin Franklin Barry et al. / Altera Corporation (San Jose, US)
A hardware system providing array conditional execution comprising:…

Apparatus and Method for Control Processing in Dual Path Processor
US 08484442 B2, July 9, 2013, Simultaneous issuance of multiple instructions, Simon Knowles / Icera Inc. (Wilmington, US)
A computer processor, the processor comprising:…

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