Featured patents

System of Rotating Data in a Plurality of Processing Elements
US 08856493 B2, Oct. 7, 2014, Application specific, Mark Beaumont / Micron Technology, Inc. (Boise, US)
An array of processing elements, comprising:…

Hierarchical Reconfigurable Computer Architecture
US 08799623 B2, Aug. 5, 2014, Reconfiguring, Joël Cambonie / STMicroelectronics S.A. (Montrouge, FR)
A reconfigurable hierarchical computer architecture having N levels, where N is…

Debugging of a Data Processing Apparatus
US 08874883 B2, Oct. 28, 2014, Specialized instruction processing in support of testing, debugging, emulation, Michael John Williams et al. / ARM Limited (Cambridge, GB)
A data processing apparatus comprising:…

Task Switch Immunized Performance Monitoring
US 08868886 B2, Oct. 21, 2014, Processing Control, Brian R. Mestan et al. / International Business Machines Corporation (Armonk, US)
A method of making performance measurements of a program executing within…

Asynchronous Pipelined Data Path With Data Transition
US 08677103 B1, March 18, 2014, Processing control for data transfer, Dror Barash / Marvell Isreal (M.I.S.L) Ltd. (Yokneam, IL
An apparatus comprising:…

Data Processor Including an Operation Unit to Execute Operations in Parallel
US 08650386 B2, Feb. 11, 2014, Decoding instruction to accommodate plural instruction interpretations, Masaitsu Nakajima et al. / Panasonic Corporation (Osaka, JP)
A data processor, comprising:…

Accepting or Rolling Back Execution of Instructions Based on Comparing Predicted and Actual Dependency Control Signals
US 08589662 B2, Nov. 19, 2013, Dynamic Instruction Dependency Checking, Monitoring or Conflict Resolution, Jude A. Rivers et al. / International Business Machines Corporation (Armonk, US)
A microprocessor for multiple instruction issue in the microprocessor,…

Register File With Circuitry for Setting Register Entries to a Predetermined Value
US 08583897 B2, Nov. 12, 2013, Instruction Decoding, Simon John Craske / ARM Limited (Cambridge, GB)
A register file comprising a plurality of register entries for storing data…

Device for Executing an Instruction Using a Target Execution Speed
US 08560812 B2, Oct. 15, 2013, Instruction Issuing, Kazuya Okamoto et al. / Toyota Jidosha Kabushiki Kaisha (Toyota-shi, JP)
A multithread execution device comprising:…

Multi-Processor Systems Communicating Using Data and Control Tokens
US 08495340 B2, July 23, 2013, Distributed processing system, James Arthur Dean Wallace Anderson
A processing apparatus comprising a plurality of processors, each arranged…

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