Featured patents

Processor Apparatus and Multithread Processor Apparatus
US 08850168 B2, Sept. 30, 2014, Context preserving (e.g., context swapping, checkpointing, register windowing, Masahide Kakeda et al. / Panasonic Corporation (Osaka, JP)
A processor apparatus comprising:…

Prefix Accumulation for Efficient Processing of Instructions With Multiple Prefix Bytes
US 08838938 B2, Sept. 16, 2014, Decoding instruction to accommodate variable length instruction or operand, John L. Duncan et al. / Via Technologies, Inc. (New Taipei, TW)
In a microprocessor that has an instruction set architecture…

Blank Bit and Processor Instructions Employing the Blank Bit
US 08806183 B1, Aug. 12, 2014, Conditional branching, Gyle D. Yearsley / IXYS CH GmbH CH
A method comprising: (a)…

Register Files for a Digital Signal Processor Operating in an Interleaved Multi-Threaded Environment
US 08713286 B2, April 29, 2014, Long instruction word, William C. Anderson et al. / QUALCOMM Incorporated (San Diego, US)
A processor device comprising:…

Allocation of Counters From a Pool of Counters to Track Mappings of Logical Registers to Physical Registers for Mapper Based Instruction Executions
US 08661230 B2, Feb. 25, 2014, Scoreboarding, reservation station, or aliasing, Gregory W. Alexander et al. / International Business Machines Corporation (Armonk, US)
A microprocessor comprising:…

Method and System for Dynamically Parallelizing Application Program
US 08650384 B2, Feb. 11, 2014, Multiprocessor instruction, Mikyung Kang et al. / Samsung Electronics Co., Ltd. (Suwon-Si, KR)
A system for dynamically parallelizing an application program, the system…

Load/Move and Duplicate Instructions for a Processor
US 08650382 B2, Feb. 11, 2014, Vector processor, Patrice Roussel / Intel Corporation (Santa Clara, US)
A processor, comprising:…

Reducing Data Hazards in Pipelined Processors to Provide High Processor Utilization
US 08612728 B2, Dec. 17, 2013, Simultaneous issuance of multiple instructions, James Peterson et al. / Micron Technology, Inc. (Boise, US)
A method of operating a pipelined computer processor, comprising:…

System and Method of Instruction Modification
US 08549266 B2, Oct. 1, 2013, Instruction modification based on condition, Eric Hao et al.
A method comprising:…

Video Instruction Processing of Desired Bytes in Multi-Byte Buffers by Shifting to Matching Byte Location
US 08473721 B2, June 25, 2013, Arithmetic operation instruction processing, Michael J. Mantor et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method for implementing a single instruction to process video data…

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