Featured patents

Non-Quiescing Key Setting Facility
US 08751775 B2, June 10, 2014, Processing control for data transfer, Christian Jacobi et al. / International Business Machines Corporation (Armonk, US)
A method of facilitating processing in a computing environment having a plurality…

Processor and Method for Distributing Load Among Plural Pipeline Units
US 08683181 B2, March 25, 2014, Processing Control, Hideki Okawara / Fujitsu Limited (Kawasaki, JP)
An arithmetic processor comprising:…

Unanimous Branch Instructions in a Parallel Thread Processor
US 08677106 B2, March 18, 2014, Evaluation of multiple conditions or multiway branching, Richard Craig Johnson et al. / Nvidia Corporation (Santa Clara, US)
A computer-implemented method for managing one or more threads of a thread group…

Systems and Method for Managing Divergent Threads in a SIMD Architecture
US 08667256 B1, March 4, 2014, Context preserving (e.g., context swapping, checkpointing, register windowing, Brett W. Coon et al. / NVIDIA Corporation (Santa Clara, US)
A computer-implemented method for managing divergent threads in a thread group…

Effective Scheduling of Producer-Consumer Processes in a Multi-Processor System
US 08621184 B1, Dec. 31, 2013, Processing Control, Prashanth Radhakrishnan et al. / NetApp, Inc. (Sunnyvale, US)
A method for data processing in a producer-consumer environment on a multi-core…

Obfuscated Hardware Multi-Threading
US 08621186 B2, Dec. 31, 2013, Processing Control, Uri Kaluzhny et al. / Cisco Technology Inc. (San Jose, US)
A method of obfuscating a multi-threaded computer program, comprising the steps…

Scalar/Vector Processor That Includes a Functional Unit With a Vector Section and a Scalar Section
US 08510534 B2, Aug. 13, 2013, Scalar / vector processor interface, Nur Engin et al. / ST-Ericsson SA (Plan-les-Ouates, CH)
A scalar/vector processor comprising:…

Instruction Length Based Cracking for Instruction of Variable Length Storage Operands
US 08495341 B2, July 23, 2013, Decoding instruction to accommodate variable length instruction or operand, Wen Li et al. / International Business Machines Corporation (Armonk, US)
A method for managing variable operand length instructions, the method…

Branch Trace History Compression
US 08489866 B2, July 16, 2013, Specialized instruction processing in support of testing, debugging, emulation, Mauricio Jose Serrano et al. / International Business Machines Corporation (Armonk, US)
A method for monitoring processing of branch instructions in a computer system,…

Instruction for Comparing Active Vector Elements to Preceding Active Elements to Determine Value Differences
US 08504806 B2, Aug. 6, 2013, Floating point or vector, Jeffry E. Gonion / Apple Inc. (Cupertino, US)
A method for generating a result vector, comprising:…

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