Featured patents

Microprocessor That Fuses Load-Alu-Store and JCC Macroinstructions
US 08856496 B2, Oct. 7, 2014, Instruction Decoding, Terry Parks et al. / Via Technologies, Inc. (New Taipei, TW)
A microprocessor configured to receive first and second program-adjacent…

Method and Apparatus for Programmable Coupling Between CPU and Co-Processor
US 08756406 B1, June 17, 2014, Loop execution, Mark Fullerton et al. / Marvell International Ltd. (Hamilton, BM)
A method for processing data, comprising:…

Processor Load Determination and Speed Control
US 08621185 B1, Dec. 31, 2013, Processing Control, Pradeep Jugraj Nemavat / Marvell International Ltd. (Hamilton, BM)
An apparatus comprising:…

Extended Register Addressing Using Prefix Instruction
US 08601239 B2, Dec. 3, 2013, Predecoding of instruction component, Ryuichi Sunayama et al. / Fujitsu Limited (Kawasaki, JP)
A processor, comprising:…

Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs
US 08589665 B2, Nov. 19, 2013, Mode switch or change, Karthick Rajamani et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for processing an instruction…

Rotate Instructions That Complete Execution Without Reading Carry Flag
US 08504807 B2, Aug. 6, 2013, Logic operation instruction processing, Maxim Loktyukhin et al. / Intel Corporation (Santa Clara, US)
A method comprising:…

Performing an Allreduce Operation on a Plurality of Compute Nodes of a Parallel Computer
US 08484440 B2, July 9, 2013, Operation, Ahmad Faraj / International Business Machines Corporation (Armonk, US)
A method of performing an allreduce operation on a plurality of compute nodes…

VLIW Processor With Execution Units Executing Instructions From Instruction Queues and Accessing Data Queues to Read and Write Operands
US 08458443 B2, June 4, 2013, Instruction Issuing, Manfred Stadler et al. / SMSC Holdings S.A.R.L. (Luxembourg, LU)
A processor for use in connection with a system memory, the processor comprising:…

Substituting Portion of Template Instruction Parameter With Selected Virtual Instruction Parameter
US 08447958 B2, May 21, 2013, Instruction modification based on condition, Kevin D. Kissell / Bridge Crossing, LLC (San Francisco, US)
A pipelined microprocessor, comprising:…

Method and Apparatus for Computing Massive Spatio-Temporal Correlations Using a Hybrid CPU-GPU Approach
US 08464026 B2, June 11, 2013, Operation, Ravishankar Rao et al. / International Business Machines Corporation (Armonk, US)
A computer system for computing massive spatio-temporal correlations, comprising:…

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