Featured patents

Scheduling Instructions in a Cascaded Delayed Execution Pipeline to Minimize Pipeline Stalls Caused by a Cache Miss
US 08812822 B2, Aug. 19, 2014, Simultaneous issuance of multiple instructions, David A. Luick / International Business Machines Corporation (Armonk, US)
A design structure embodied in a non-transitory machine readable storage device…

Very Long Instruction Word (VLIW) Computer Having Efficient Instruction Code Format
US 08738892 B2, May 27, 2014, Long instruction word, Takahiro Kageyama et al. / Panasonic Corporation (Osaka, JP)
A very long instruction word (VLIW) processor which performs a plurality…

Cache Collaboration Method, Apparatus, and System
US 08719552 B2, May 6, 2014, Microprocessor or multichip or multimodule processor having sequential program control, Youshui Long / Huawei Technologies Co., Ltd. (Shenzhen, CN)
A cache collaboration method, comprising:…

Method of Program Obfuscation and Processing Device for Executing Obfuscated Programs
US 08621187 B2, Dec. 31, 2013, Conditional branching, Marc Vauclair / NXP, B.V. (Eindhoven, NL)
A method of converting a program of instructions for a programmable processor,…

Performing a Deterministic Reduction Operation in a Parallel Computer
US 08601237 B2, Dec. 3, 2013, Operation, Brian E. Smith et al. / International Business Machines Corporation (Armonk, US)
A method of performing a deterministic reduction operation in a parallel…

Direct Injection of Data to Be Transferred in a Hybrid Computing Environment
US 08578133 B2, Nov. 5, 2013, Including coprocessor, Joseph D. Ratterman et al. / International Business Machines Corporation (Armonk, US)
A method of direct injection of data to be transferred in a hybrid computing…

Method and Apparatus for Universal Logical Operations Utilizing Value Indexing
US 08539206 B2, Sept. 17, 2013, Logic operation instruction processing, Andrew T. Forsyth / Intel Corporation (Santa Clara, US)
A method for performing a logical operation on a computer processor comprising:…

Configuring Plural Cores to Perform an Instruction Having a Multi-Core Characteristic
US 08495342 B2, July 23, 2013, Floating point or vector, Robert H. Bell, Jr. et al. / International Business Machines Corporation (Armonk, US)
A method for re-configuration of a processor having plural cores, the method…

Dynamic Reconfiguration Support Apparatus, Dynamic Reconfiguration Support Method, and Computer Product
US 08495339 B2, July 23, 2013, Reconfiguring, Tatsuya Yamamoto / Fujitsu Limited (Kawasaki, JP)
A non-transitory computer-readable recording medium storing therein…

Microprocessor Integrated Circuit With First Processor That Outputs Debug Information in Response to Reset by Second Processor of the Integrated Circuit
US 08464032 B2, June 11, 2013, Specialized instruction processing in support of testing, debugging, emulation, G. Glenn Henry et al. / VIA Technologies, Inc. (New Taipei, TW)
A microprocessor integrated circuit, comprising:…

Patentorg has 542 documents under Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors) Patents.

Narrow down the browsing criteria below to see more patents.

Select a subcategory
Quick navigation
New documents
  • Process for the Production of the Actinobacillus Pleuropneumoniae Toxins APXI or APXIII in a Liquid Culture Medium Under Supply of Air Enriched in Carbon Dioxide
  • Method for Manufacturing Nonvolatile Memory Device
  • Supply Chain Demand Satisfaction
  • Supply-Line Management Device
  • Storage Control Device and Method for Managing Snapshot