Featured patents

Central Processor for Memory Tag
US 08856497 B2, Oct. 7, 2014, Decoding instruction to accommodate variable length instruction or operand, Fraser John Dickin et al. / Hewlett-Packard Development Company, L.P. (Houston, US)
A processor comprising:…

Program Flow Control for Multiple Divergent SIMD Threads Using a Minimum Resume Counter
US 08832417 B2, Sept. 9, 2014, Conditional branching, Andrew E. Gruber et al. / QUALCOMM Incorporated (San Diego, US)
A method for controlling a processor comprising:…

Method and Apparatus for Unpacking and Moving Packed Data
US 08793475 B2, July 29, 2014, Byte-Word Rearranging, Bit-Field Insertion or Extraction, String Length Detecting, or Sequence Detecting, Benny Eitan et al. / Intel Corporation (Santa Clara, US)
An apparatus comprising:…

Cache Memory Control Device, Semiconductor Integrated Circuit, and Cache Memory Control Method
US 08713291 B2, April 29, 2014, Processing control for data transfer, Naoya Ishimura / Fujitsu Limited (Kawasaki, JP)
A cache memory control device, comprising:…

Intermediate Register Mapper
US 08683180 B2, March 25, 2014, Scoreboarding, reservation station, or aliasing, Lee E. Eisen et al. / International Business Machines Corporation (Armonk, US)
A method for administering physical registers in multiple physical register sets…

Extending Operations of an Application in a Data Processing System
US 08555033 B2, Oct. 8, 2013, Architecture Based Instruction Processing, Ritchard L. Schacher et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for extending operations…

Computing Apparatus and Method of Handling Interrupt
US 08495345 B2, July 23, 2013, Loop execution, Yeon-gon Cho et al. / Samsung Electronics Co., Ltd. (Suwon-si, KR)
A computing apparatus, comprising:…

Accessing Value for Local Variable From Function Call Stack Upon Offset Matching With Instruction Extracted Stack Pointer Offset or From Cache
US 08478970 B2, July 2, 2013, Processing control for data transfer, Young Su Kwon et al. / Electronics and Telecommunications Research Institute (Daejeon, KR)
An apparatus for accessing a memory according to a processor instruction,…

Processor Architecture for Exact Pointer Identification
US 08473722 B2, June 25, 2013, Processing control for data transfer, Matthias Meyer / Universitaet Stuttgart (Stuttgart, DE)
A processor architecture in which the access to a memory occurs via pointers…

Coprocessor Interface Architecture and Methods of Operating the Same
US 08447957 B1, May 21, 2013, Processing control for data transfer, Sivakumar Velusamy et al. / Xilinx, Inc. (San Jose, US)
A system, comprising:…

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