Featured patents

Multifunction Hexadecimal Instruction Form System and Program Product
US 08838942 B2, Sept. 16, 2014, Floating point or vector, Eric M. Schwarz et al. / International Business Machines Corporation (Armonk, US)
A method for performing combinations of multiply, add, and subtract operations…

Blank Bit and Processor Instructions Employing the Blank Bit
US 08806183 B1, Aug. 12, 2014, Conditional branching, Gyle D. Yearsley / IXYS CH GmbH CH
A method comprising: (a)…

Task Switch Immunized Performance Monitoring
US 08868886 B2, Oct. 21, 2014, Processing Control, Brian R. Mestan et al. / International Business Machines Corporation (Armonk, US)
A method of making performance measurements of a program executing within…

Apparatus and Method for Disabling a Microprocessor That Provides for a Secure Execution Mode
US 08607034 B2, Dec. 10, 2013, Branching, G. Glenn Henry et al. / VIA Technologies, Inc. (New Taipei, TW)
An apparatus providing for a secure execution environment, comprising:…

Hardware Device for Processing the Tasks of an Algorithm in Parallel
US 08607031 B2, Dec. 10, 2013, Instruction Issuing, Patrick Michel et al. / International Business Machines Corporation (Armonk, US)
A hardware device for concurrently processing a fixed set of predetermined tasks…

Methods and Apparatus for Matrix Decompositions in Programmable Logic Devices
US 08555031 B2, Oct. 8, 2013, Systolic array processor, Michael Fitton / Altera Corporation (San Jose, US)
A processor for QR-decomposition, the processor comprising a boundary cell…

Accelerating Parallel Transactions Using Cache Resident Transactions
US 08533440 B2, Sept. 10, 2013, Mode switch or change, Jan S. Gray et al. / Microsoft Corporation (Redmond, US)
In a computing environment comprising a hardware assisted transaction system,…

Semiconductor Device and Data Processing System Selectively Operating as One of a Big Endian or Little Endian System
US 08504801 B2, Aug. 6, 2013, Instruction Alignment, Yuri Azuma et al. / Renesas Electronics Corporation (Kawasaki-shi, JP)
A cellular phone comprising:…

Methods and Apparatuses for Efficient Load Processing Using Buffers
US 08452946 B2, May 28, 2013, Dynamic Instruction Dependency Checking, Monitoring or Conflict Resolution, Herbert H. Hum et al. / Intel Corporation (Santa Clara, US)
A method comprising:…

Running Subtract and Running Divide Instructions for Processing Vectors
US 08447956 B2, May 21, 2013, Floating point or vector, Keith E. Diefendorff et al. / Apple Inc. (Cupertino, US)
A method for generating a result vector with subtracted values from a first input…

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