Featured patents

Implementing Vector Memory Operations
US 08707012 B2, April 22, 2014, Vector processor operation, Joel Emer et al. / Intel Corporation (Santa Clara, US)
A processor comprising:…

Processor Configured for Operation With Multiple Operation Codes Per Instruction
US 08700886 B2, April 15, 2014, Instruction Decoding, Jacob Mathews et al. / Agere Systems LLC (Allentown, US)
A processor comprising:…

Parsing-Enhacement Facility
US 08583899 B2, Nov. 12, 2013, Instruction Decoding, Dan F. Greiner et al. / International Business Machines Corporation (Armonk, US)
A computer program product for executing an extended translate and test…

Extending Operations of an Application in a Data Processing System
US 08555033 B2, Oct. 8, 2013, Architecture Based Instruction Processing, Ritchard L. Schacher et al. / International Business Machines Corporation (Armonk, US)
A method, in a data processing system, for extending operations…

Processing Vectors Using Wrapping Shift Instructions in the Macroscalar Architecture
US 08549265 B2, Oct. 1, 2013, Floating point or vector, Jeffry E. Gonion / Apple Inc. (Cupertino, US)
A method, comprising:…

Central Processing Unit and Microcontroller
US 08516225 B2, Aug. 20, 2013, Instruction Fetching, Masami Fukushima et al.
A central processing unit, comprising a control circuit for reading a program…

Embedding Global Barrier and Collective in Torus Network With Each Node Combining Input From Receivers According to Class Map for Output to Senders
US 08521990 B2, Aug. 27, 2013, Distributed processing system, Yutaka Sugawara et al. / International Business Machines Corporation (Armonk, US)
A method of embedding a global barrier and global interrupt network in a parallel…

Processor Including Age Tracking of Issue Queue Instructions
US 08489863 B2, July 16, 2013, Instruction Issuing, Maureen Anne Delaney et al. / International Business Machines Corporation (Armonk, US)
A method of processing instructions, comprising:…

Methods and Apparatuses for Efficient Load Processing Using Buffers
US 08452946 B2, May 28, 2013, Dynamic Instruction Dependency Checking, Monitoring or Conflict Resolution, Herbert H. Hum et al. / Intel Corporation (Santa Clara, US)
A method comprising:…

Redirection Table and Predictor for Fetching Instruction Routines in a Virtual Machine Guest
US 08464028 B2, June 11, 2013, Instruction Fetching, Anton Chernoff et al. / Advanced Micro Devices, Inc. (Sunnyvale, US)
A method comprising:…

Patentorg has 542 documents under Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors) Patents.

Narrow down the browsing criteria below to see more patents.

Select a subcategory
Quick navigation
New documents
  • Process for the Production of the Actinobacillus Pleuropneumoniae Toxins APXI or APXIII in a Liquid Culture Medium Under Supply of Air Enriched in Carbon Dioxide
  • Method for Manufacturing Nonvolatile Memory Device
  • Supply Chain Demand Satisfaction
  • Supply-Line Management Device
  • Storage Control Device and Method for Managing Snapshot