Featured patents

Performance Enhancement of Address Translation Using Translation Tables Covering Large Address Spaces
US 08843727 B2, Sept. 23, 2014, Segment or page table descriptor, Koichi Yamada et al. / Intel Corporation (Santa Clara, US)
A method comprising:…

Crash-Tolerant Incremental Change Tracking Between Backups of a Source Storage
US 08719521 B1, May 6, 2014, Archiving, Maxim Shatskikh et al. / Storagecraft Technology Corporation (Draper, US)
A method of crash-tolerant incremental change tracking between backups…

Memory Controller, Method of Controlling Unaligned Memory Access, and Computing Apparatus Incorporating Memory Controller
US 08688891 B2, April 1, 2014, For multiple memory modules, Il-Hyun Park et al. / Samsung Electronics Co., Ltd. (Suwon-si, KR)
A computing apparatus, comprising:…

Competition Testing Device
US 08667233 B2, March 4, 2014, Control technique, Yasushi Asano / Fujitsu Limited (Kawasaki, JP)
A competition testing apparatus for testing an access competition…

Method and Apparatus for Accessing a Tape Drive From a Plurality of Nodes
US 08612701 B1, Dec. 17, 2013, Backup, Adonijah Park et al. / Symantec Corporation (Mountain View, US)
A method comprising:…

Storage Controller and Virtual Volume Control Method
US 08606993 B2, Dec. 10, 2013, Arrayed, Yutaro Kawaguchi et al. / Hitachi, Ltd. (Tokyo, JP)
A storage system being coupled to a host computer, comprising:…

Systems and Methods for Variable Level Use of a Multi-Level Flash Memory
US 08560765 B2, Oct. 15, 2013, Programmable read only memory (PROM, EEPROM, etc.), Robert W. Warren / LSI Corporation (San Jose, US)
An electronic system, the system comprising:…

Apparatus and Method of Reducing Page Fault Rate in Virtual Memory System
US 08543791 B2, Sept. 24, 2013, Directories and tables, Ji-hyun In et al. / Samsung Electronics Co., Ltd. (Suwon-si, KR)
An apparatus for reducing a page fault rate in a virtual memory system,…

Reporting Logical Sector Alignment for ATA Mass Storage Devices
US 08516190 B1, Aug. 20, 2013, Arrayed, Rakesh Narayan Iyer / NVIDIA Corporation (Santa Clara, US)
A method of reporting logical sector alignment for an ATA mass storage device,…

Hybrid Storage System for a Multi-Level Raid Architecture
US 08484415 B2, July 9, 2013, Arrayed, Byungcheol Cho / Taejin Info Tech Co., Ltd. (Seoul, KR)
A hybrid storage system for a multi-level RAID architecture, comprising:…

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