Featured patents

Programmable Interrupt Routing System
US 08838852 B1, Sept. 16, 2014, Input / Output interrupting, Haneef Mohammed et al. / Cypress Semiconductor Corporation (San Jose, US)
A method comprising:…

Storage System With Multicast DMA and Unified Address Space
US 08819304 B2, Aug. 26, 2014, Programmed control memory accessing, William H. Moore et al. / DSSD, Inc. (Menlo Park, US)
A method for writing data, comprising:…

Information Processing Apparatus, Driver Setting Method, and Storage Medium
US 08799524 B2, Aug. 5, 2014, Peripheral configuration, Yukie Nomura / Canon Kabushiki Kaisha (Tokyo, JP)
An information processing apparatus for managing a plurality of devices,…

Semiconductor Device and Control Method
US 08782301 B2, July 15, 2014, Timing, Taro Shibata / Fujitsu Semiconductor Limited (Yokohama, JP)
A semiconductor device comprising:…

Secure KVM Device Ensuring Isolation of Host Computers
US 08769172 B2, July 1, 2014, Via common units and peripheral-specific units, Oleg Vaisband et al. / High Sec Labs Ltd. (Yokneam, IL)
An isolated KVM device that permits sharing of peripherals between multiple…

Transactional Memory That Performs an Atomic Metering Command
US 08775686 B2, July 8, 2014, Input / Output command process, Gavin J. Stark / Netronome Systems, Incorporated (Santa Clara, US)
A method comprising: (a)…

Information Processing Apparatus for Conducting Security Processing and Security Processing Method
US 08688863 B2, April 1, 2014, Concurrently performing Input / Output operation and other operation unrelated to Input / Output, Isamu Yamada et al. / Fujitsu Limited (Kawasaki, JP)
An information processing apparatus that executes security processing…

Interrupt Techniques
US 08645596 B2, Feb. 4, 2014, Input / Output data buffering, Steven King et al. / Intel Corporation (Santa Clara, US)
A method comprising:…

Bus Arbitration Techniques to Reduce Access Latency
US 08539129 B2, Sept. 17, 2013, Access prioritizing, Feng Wang / QUALCOMM Incorporated (San Diego, US)
A method of arbitrating requests from bus masters for access to shared memory…

Mechanism for a Shared Serial Peripheral Interface
US 08463968 B2, June 11, 2013, Centralized bus arbitration, Michael Derr et al. / Intel Corporation (Santa Clara, US)
A chipset comprising:…

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