Hierarchical or multilevel accessing - Electrical computers and digital data processing systems: input / output patents
Featured patents
Hierarchical Multi-Tenancy Support for Host Attachment Configuration Through Resource Groups
US 08683103 B2, March 25, 2014, Richard A. Ripberger / International Business Machines Corporation (Armonk, US)
A system of hierarchy multi-tenancy support for configuration of a plurality…
Hierarchical Multi-Tenancy Support for Host Attachment Configuration Through Resource Groups
US 08683104 B2, March 25, 2014, Richard A. Ripberger / International Business Machines Corporation (Armonk, US)
A method of hierarchy multi-tenancy support for configuration of a plurality…
Patentorg has 2 documents under Hierarchical or Multilevel Accessing Patents.
- Input / Output Data Processing 8
- Input / Output Expansion 14
- Input / Output Addressing 29
- Address Data Transfer 9
- Input / Output Command Process 100
- Operation Scheduling 12
- Concurrently Performing Input / Output Operation and Other Operation Unrelated to Input / Output 9
- Peripheral Configuration 104
- Address Assignment 24
- Configuration Initialization 26
- Protocol Selection 14
- As Input or Output 4
- By Detachable Memory 7
- Mode Selection 33
- Peripheral Monitoring 55
- Characteristic Discrimination 33
- Availability Monitoring 17
- Activity Monitoring 20
- Status Updating 15
- Concurrent Input / Output Processing and Data Transfer 8
- Concurrent Data Transferring 2
- Direct Memory Accessing (DMA) 68
- Programmed Control Memory Accessing 7
- By Command Chaining 4
- Timing 4
- Using Addressing 8
- Via Separate Bus 1
- With Access Regulating 3
- Flow Controlling 19
- Frame Forming 14
- Transfer Direction Selection 5
- Transfer Termination 6
- Data Transfer Specifying 39
- Transferred Data Counting 7
- Burst Data Transfer 4
- Input / Output Access Regulation 34
- Access Dedication 2
- Path Selection 28
- Access Request Queuing 12
- Access Prioritization 4
- Time-Slot Accessing 1
- Input / Output Polling 2
- Input / Output Interrupting 11
- Accessing via a Multiplexer 2
- Input / Output Data Buffering 80
- Alternately Filling or Emptying Buffers 15
- Queue Content Modification 9
- Contents Validation 4
- Buffer Space Allocation or Deallocation 16
- Fullness Indication 12
- Input / Output Process Timing 8
- Processing Suspension 2
- Transfer Rate Regulation 8
- Synchronous Data Transfer 12
- Peripheral Adapting 68
- Universal 14
- Via Common Units and Peripheral-Specific Units 7
- Input / Output Data Modification 12
- Width Conversion 3
- Keystroke Interpretation 6
- Data Compression and Expansion 11
- Analog-To-Digital or Digital-To-Analog 5
- Digital-To-Digital 2
- Serial-To-Parallel or Parallel-To-Serial 15
- Application-Specific Peripheral Adapting 16
- For User Input Device 8
- For Data Storage Device 46
- Intrasystem Connection 15
- Bus Expansion or Extension 14
- Card Insertion 31
- Hot Insertion 12
- Docking Station 17
- Hot Docking 2
- System Configuring 37
- Protocol 26
- Using Transmitter and Receiver 8
- Bus Access Regulation 17
- Bus Polling 3
- Bus Master / Slave Controlling 58
- Rotational Prioritizing 3
- Bus Request Queuing 4
- Centralized Bus Arbitration 14
- Dynamic Bus Prioritization 3
- Time-Slotted Bus Accessing 4
- Delay Reduction 2
- Time-Slotted Bus Accessing 2
- Bus Interface Architecture 33
- Bus Bridge 26
- Variable or Multiple Bus Width 8
- Direct Memory Access 7
- Arbitration 2
- Buffer or Que Control 16
- Intelligent Bridge 19
- Multiple Bridges 4
- Peripheral Bus Coupling 50
- Common Protocol 9
- Different Protocol 24
- Path Selecting Switch 48
- Crossbar 12
- Access Locking 9
- Access Polling 1
- Access Arbitrating 12
- Centralized Arbitrating 7
- Decentralized Arbitrating 4
- Hierarchical or Multilevel Arbitrating 5
- Access Prioritizing 8
- Interrupt Processing 25
- Multimode Interrupt Processing 5
- Interrupt Inhibiting or Masking 12
- Interrupt Queuing 4
- Interrupt Prioritizing 4
- Programmable Interrupt Processing 5
- Processor Status 13
- Source or Destination Identifier 3
- Handling Vector 3