Featured patents

Method for Making a Current-Perpendicular-To-The-Plane (CPP) Magnetoresistive Sensor Having a Low-Coercivity Reference Layer
US 08852963 B2, Oct. 7, 2014, Having Magnetic or Ferroelectric Component, Matthew J. Carey et al. / HGST Netherlands B.V. (Amsterdam, NL)
A method for making a current-perpendicular-to-the-plane (CPP) magnetoresistive…

Method for Transferring a Layer From a Donor Substrate Onto a Handle Substrate
US 08728913 B2, May 20, 2014, Thinning of semiconductor substrate, Aziz Alami-Idrissi et al. / Soitec (Bernin, FR)
A method of transferring a layer from a donor substrate onto a handle substrate…

Critical Concentration in Etching Doped Poly Silicon With HF/HNO 3
US 08716145 B2, May 6, 2014, Silicon, Shuogang Huang / Intermolecular, Inc. (San Jose, US)
A method to etch doped polysilicon comprising…

Display Device, Organic Light Emitting Diode Display, and Manufacturing Method of Sealing Substrate
US 08617932 B2, Dec. 31, 2013, Metallic housing or support, Jung-Min Lee et al. / Samsung Display Co., Ltd. KR
A display device comprising:…

Method for Forming N-Shaped Bottom Stress Liner
US 08557668 B2, Oct. 15, 2013, Dielectric isolation formed by grooving and refilling with dielectric material, Vara Govindeswara Reddy Vakada et al. / GLOBALFOUNDRIES SINGAPORE Pte. Ltd. (Singapore, SG)
A method comprising:…

Method of Fabricating Semiconductor Device Having Buried Wiring and Related Device
US 08557691 B2, Oct. 15, 2013, Forming buried region, Byung-Gook Park et al. / Samsung Electronics Co., Ltd. (Gyeonggi-Do, KR)
A method of fabricating a semiconductor device, comprising:…

Memory Cell That Includes a Carbon-Based Memory Element and Methods of Forming the Same
US 08536015 B2, Sept. 17, 2013, Trench capacitor, Roy E. Scheuerlein et al. / SanDisk 3D LLC (Milpitas, US)
A method of forming a metal-insulator-metal (“MIM”) stack, the method comprising:…

Method for Producing Chip Elements Equipped With Wire Insertion Grooves
US 08445328 B2, May 21, 2013, Metallic housing or support, Régis Taillefer et al. / Commissariat a l'Energie Atomique et aux Energies Alternatives (Paris, FR)
A method for producing chip elements provided with a groove, comprising…

Method of Manufacturing a Semiconductor Device
US 08455325 B2, June 4, 2013, Having elevated source or drain, Yosuke Shimamune et al. / Fujitsu Semiconductor Limited (Yokohama, JP)
A method of manufacturing a semiconductor device comprising:…

Structure and Process for Metallization in High Aspect Ratio Features
US 08450204 B2, May 28, 2013, At least one layer forms a diffusion barrier, Fenton R. McFeely et al. / International Business Machines Corporation (Armonk, US)
A method of fabricating a semiconductor structure comprising:…

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