Featured patents

ADC-based Mixed-Mode Digital Phase-Locked Loop
US 08553827 B2, Oct. 8, 2013, Gang Zhang / Qualcomm Incorporated (San Diego, US)
A Phase-Locked Loop (PLL) circuit, comprising:…

Clock and Data Recovery Circuit
US 08699649 B2, April 15, 2014, Sang Jin Byun / Dongguk University Industry-Academic Cooperation Foundation (Seoul, KR)
A clock and data recovery circuit, comprising:…

Clock and Data Recovery Using LC Voltage Controlled Oscillator and Delay Locked Loop
US 08588358 B2, Nov. 19, 2013, Chan-Hong Chern et al. / Taiwan Semiconductor Manufacturing Company, Ltd. TW
A clock and data recovery (CDR) circuit, comprising:…

Frequency Synthesis System With Self-Calibrated Loop Stability and Bandwidth
US 08509369 B2, Aug. 13, 2013, Chun-Liang Chen et al. / Sunplus Technology Co., Ltd. (Hsinchu, TW)
A frequency synthesis system with self-calibrated loop stability and bandwidth,…

System and Method for Reducing Lock Acquisition Time of a Phase-Locked Loop
US 08599985 B2, Dec. 3, 2013, Rizwan Ahmed / Intel IP Corporation (Santa Clara, US)
A phase-locked loop comprising:…

Variable Delay Circuit and Delay-Locked Loop Including the Same
US 08451970 B2, May 28, 2013, Chul Woo Kim et al. / Korea University Research and Business Foundation (Seoul, KR)
A variable delay circuit comprising:…

Patentorg has 6 documents under With Charge Pump or Up and Down Counters Patents.

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