Featured patents

Digit Line Equilibration Using Access Devices at the Edge of Sub-Arrays
US 08760950 B2, June 24, 2014, Complementing / balancing, Werner Juengling / Micron Technology, Inc. (Boise, US)
An apparatus, comprising:…

Non-Volatile Semiconductor Memory Device
US 08743611 B2, June 3, 2014, Bank or block architecture, Takeshi Hioka / Kabushiki Kaisha Toshiba (Tokyo, JP)
A non-volatile semiconductor memory device comprising:…

Drift-Insensitive or Invariant Material for Phase Change Memory
US 08737121 B2, May 27, 2014, Amorphous (electrical), Glenn J. Martyna et al. / International Business Machines Corporation (Armonk, US)
A method of storing a bit at a memory device, comprising:…

Internal Voltage Generating Circuit of Phase Change Random Access Memory Device and Method Thereof
US 08625380 B2, Jan. 7, 2014, Powering, Yoon-Jae Shin / SK Hynix Inc. (Gyeonggi-do, KR)
A method for generating an internal voltage of a phase change memory device,…

Nonvolatile Semiconductor Memory Device
US 08582345 B2, Nov. 12, 2013, Resistive, Koji Hosono / Kabushiki Kaisha Toshiba (Tokyo, JP)
A nonvolatile semiconductor memory device comprising:…

Method of Testing Data Retention of a Non-Volatile Memory Cell Having a Floating Gate
US 08576648 B2, Nov. 5, 2013, Testing, Alexander Kotov et al. / Silicon Storage Technology, Inc. (San Jose, US)
A method of testing a non-volatile memory cell having a floating gate…

Non-Volatile Memory Device With Plural Reference Cells, and Method of Setting the Reference Cells
US 08559228 B2, Oct. 15, 2013, Reference signal, Thuan T. Vu et al. / Silicon Storage Technology, Inc. (San Jose, US)
A method of programming a first plurality of reference cells in a memory device…

Input Buffer Circuit, Semiconductor Memory Device and Memory System
US 08531910 B2, Sept. 10, 2013, Initiating signal, Hyoung-Seok Kim et al. / Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR)
An input buffer circuit of a semiconductor memory device, comprising:…

Semiconductor Memory Device
US 08508977 B2, Aug. 13, 2013, Resistive, Yoshihiro Ueda / Kabushiki Kaisha Toshiba (Tokyo, JP)
A semiconductor memory device comprising:…

Cell Array for Highly-Scalable, Byte-Alterable, Two-Transistor FLOTOX EEPROM Non-Volatile Memory
US 08462553 B2, June 11, 2013, Reference signal, Fu-Chang Hsu et al. / Aplus Flash Technology, Inc. (San Jose, US)
A two-transistor FLOTOX EEPROM cell that prevents punch-through and high voltage…

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