Featured patents

Light Emitting Device Package and Manufacturing Method Thereof
US 08841693 B2, Sept. 23, 2014, With housing or contact structure, Young Hee Song et al. / Samsung Electronics Co., Ltd. (Suwon-Si, KR)
A light emitting device package, comprising:…

Semiconductor Device and Related Fabrication Methods
US 08748981 B2, June 10, 2014, In integrated circuit structure, Jiang-Kai Zuo et al. / Freescale Semiconductor, Inc. (Austin, US)
A semiconductor device structure comprising:…

Manufacturing Method of Semiconductor Device, and Semiconductor Device
US 08742559 B2, June 3, 2014, Housing or Package, Noriyuki Takahashi / Renesas Electronics Corporation (Kanagawa, JP)
A manufacturing method of a semiconductor device, comprising the steps of:…

Methods for Wafer-Level Packaging of Microfeature Devices and Microfeature Devices Formed Using Such Methods
US 08704380 B2, April 22, 2014, Chip mounted on chip, Warren M. Farnworth et al. / Micron Technology, Inc. (Boise, US)
A microfeature assembly, comprising:…

Method for Manufacturing Semiconductor Device
US 08704219 B2, April 22, 2014, Semiconductor Is an Oxide of a Metal or Copper Sulfide, Hiromichi Godo et al. / Semiconductor Energy Laboratory Co., Ltd. (Atsugi-shi, Kanagawa-ken, JP)
A semiconductor device comprising:…

Method to Increase Breakdown Voltage of Semiconductor Devices
US 08692293 B2, April 8, 2014, Doping on side of heterojunction with lower carrier affinity), Vinod Adivarahan et al. / University of South Carolina (Columbia, US)
A semiconductor device comprising:…

Variable Impedance Memory Element Structures, Methods of Manufacture, and Memory Devices Containing the Same
US 08624219 B1, Jan. 7, 2014, With specified electrode composition or configuration, Foroozan Sarah Koushan et al. / Adesto Technologies Corporation (Sunnyvale, US)
A memory device, comprising:…

Multi-Function and Shielded 3D Interconnects
US 08610259 B2, Dec. 17, 2013, With particular lead geometry, Piyush Savalia et al. / Tessera, Inc. (San Jose, US)
A microelectronic unit, comprising:…

Wafer-Leveled Chip Packaging Structure and Method Thereof
US 08587091 B2, Nov. 19, 2013, With peripheral feature due to separation of smaller semiconductor chip from larger wafer, Yu-Hua Chen et al. / Invensas Corporation (San Jose, US)
A semiconductor packaging structure, comprising:…

Tunnel FET and Methods for Forming the Same
US 08471329 B2, June 25, 2013, Short channel insulated gate field effect transistor, Matthias Passlack et al. / Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW)
A tunnel field-effect transistor (TFET) comprising:…

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